In this paper , a clock recovery system that based on phase control technology is studied 本文設(shè)計(jì)的鎖相環(huán)路是基于相位控制技術(shù)的時(shí)鐘恢復(fù)系統(tǒng)。
The clock recovery system is fabricated in tsmc 0 . 25um cmos process . simulation in smartspice shows that the circuit as expected 設(shè)計(jì)中采用tsmc0 . 25umcmos工藝,用smartspice進(jìn)行設(shè)計(jì)仿真和優(yōu)化。
In the last part of this paper , simulation is given to show the performances of the clock recovery methods . the results prove the good jitter performances of the methods 從仿真結(jié)果可以看出,同步時(shí)鐘統(tǒng)計(jì)恢復(fù)法具有很好的抖動(dòng)性能,可以作為gpon系統(tǒng)tdm接入的一種高效時(shí)鐘恢復(fù)方案。
Clock recovery is an important and difficult part of tdm access , so the thesis will emphasize on it . and two methods of clock recovery are proposed in the thesis 然后,本文對同步時(shí)鐘統(tǒng)計(jì)恢復(fù)法進(jìn)行了分析,推導(dǎo)出了時(shí)鐘信號(hào)低頻抖動(dòng)的時(shí)域和頻域特性公式,并利用matlab對低頻特性進(jìn)行了仿真分析。